1. Field of Invention
The present invention relates to a substrate of a multilayer structure, especially a TFT substrate, and a substrate having a planarization layer suitable for a liquid crystal device, etc. using the TFT substrate and a manufacturing method thereof, and a substrate for an electro-optical device, and an electro-optical device.
2. Description of Related Art
A liquid crystal device is constructed by filling liquid crystal between two sheets of substrates, such as a glass substrate or quartz substrate. A liquid crystal device can display images by providing active elements, such as a thin film transistor (hereinafter referred to as TFT) and pixel electrodes in a matrix shape on one substrate and counter electrodes (transparent electrodes (ITO (indium tin oxide))) on the other substrate, and changing optical properties of the liquid crystal layer filled between both substrates in response to image signals.
An electro-optical device, such as an active matrix addressed liquid crystal device using active elements, is configured by providing pixel electrodes and switching elements on a substrate (an active matrix substrate) to correspond to each intersection of a plurality of scan lines (gate lines) and data lines (source lines) which are arranged in longitudinal and transverse directions, respectively.
A switching element, such as a TFT element, is turned on by an ON signal applied to a gate line and writes an image signal applied through a source line into a pixel electrode (a transparent electrode (ITO)). In this way, voltage based on an image signal is applied to a liquid crystal layer between a pixel electrode and a counter electrode, thereby changing the array of liquid crystal molecules. In this way, a transmittance ratio of a pixel changes, and light passing through a pixel electrode and a liquid crystal layer changes according to the image signal, thereby performing image display.
Meanwhile, in a case where each element constituting an element substrate, such as a TFT substrate, is provided on one plane of a substrate, the occupying area of the element increases and the area of a pixel electrode part decreases, thus reducing the aperture ratio of a pixel. Therefore, in the related art a stacked structure has employed such that each element is divided into a plurality of layers and each film formation layer is electrically isolated by disposing an interlayer insulating film between each layer (film formation layer).
That is, an element substrate is constructed by stacking each film formation layer, such as a semiconductor thin film, an insulating thin film, or a conductive thin film with a predetermined pattern on a glass or quartz substrate. A TFT substrate is formed by repeatedly performing a variety of film formation steps and a photolithography step over every film formation layer. For instance, on a TFT substrate, film formation layers, such as a semiconductor layer, constituting a channel of a TFT element, a wiring layer, such as a data line, and a pixel electrode layer formed of an ITO film are stacked.
However, according to a film formation pattern of each layer, the surface of a stacked structure of film formation layers has irregularities. When such irregularities occur in a layer being in contact with a liquid crystal layer, defects tend to occur in the alignment of liquid crystal. Thus, in a lower layer of a layer adjacent to a liquid crystal layer, an interlayer insulating film may be planarized. For instance, an interlayer insulating film forming a lower layer of a pixel electrode layer is polished and planarized by CMP (chemical mechanical polishing) or the like.
While the variation in thickness of the respective layers falls within approximately 5% when CMP is not performed, the film thickness of the interlayer insulating film changes every portion thereof according to the irregularities of a film formation pattern, when CMP is performed. In this case, the variation in the film thickness reaches even 20-30%. When two film formation patterns on and beneath the interlayer insulating film are connected to each other, a contact hole is formed by making an opening in the interlayer insulating film and, through the contact hole, two film formation patterns on and beneath the interlayer insulating film are electrically connected to each other. Two or more types of film formation patterns may be formed in the same film formation layer, and two or more contact holes may be formed in a single interlayer insulating film.
When an interlayer insulating film is planarized by CMP, a contact hole formed in a relatively thicker portion of the interlayer insulating film is made different in depth from a contact hole formed in a thinner portion thereof. In this case, in etching to make an opening in the interlayer insulating film, only a shorter contact hole is completely opened. A longer contact hole is not completely opened by performing an etching step once. When the longer contact hole is completely opened, grounding wires of a lower layer to be connected through a shorter contact hole may be completely etched to be removed in an over-etching step. Specifically, a problem occurs that a plurality of contact holes formed in an interlayer insulating film are not opened by performing an etching step once when the interlayer insulating film is planarized by CMP.
Further, a situation occurs that when an interlayer insulating film is planarized by CMP, a portion of an interlayer insulating film becomes relatively thicker compared to the case where an interlayer insulating film is not planarized by CMP. When a contact hole is formed in the thick portion of the interlayer insulating film, the ratio of the depth of a contact hole to the length of bottom side of a contact hole, i.e., an aspect ratio, may be made relatively large. In this case, a problem occurs that the adhesion of a metal film in a contact hole becomes poor so that contact characteristics are deteriorated.